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Folded Filter
Folded Filter Description
The folded (semi-parallel) single rate CoreFIR type implements the general FIR filter EQ 1 on page 5 . The
folded filter utilizes a minimal number of MAC blocks that are sufficient to keep up with an average input
sample rate. CoreFIR automatically generates the semi-parallel filter type, if the FPGA clock frequency is at
least two times bigger than the input sample frequency. Figure 3 on page 9 shows the simplified block
diagram of the folded filter.
If the clock to sample rate ratio is equal or more than the number N of filter coefficients, the folded filter
utilizes a single MAC block.
Folded Filter Interface
Parameters or Generics
Folded CoreFIR RTL has parameters (Verilog) or generics (VHDL), described in Table 8 . All the parameters
and generics are positive integer types. The table shows a superset of the parameters used by all FIR filter
types while indicating which parameters the folded type utilizes.
Table 8 · Semi-Parallel CoreFIR Parameter or Generic Descriptions
Parameter Name
Valid
Default
Description
Range
CFG_ARCH
1-4
1
Filter type:
1: Fully Enumerated
2: Folded
3: Polyphase Interpolator
4 : Polyphase Decimator
TAPS
COEF_TYPE
2-1024
0-1
16
0
Number of taps
0: Constant coefficients (including multiple coefficient sets).
1: Reloadable coefficients.
COEF_SETS
1-16
1
1: Single coefficient set.
2-16: Multiple coefficient sets.
Valid when constant coefficient type is selected (COEF_TYPE==0).
COEF_SYMM
COEF_UNSIGN
0-2
0-1
0
0
Folded filter does not use the parameter.
0: Signed coefficients.
1: Unsigned coefficients.
COEF_WIDTH
2-18
12
Coefficient bit width. Signed coefficient width ranges from 2 to 18 bits;
unsigned from 2 to 17 bits.
DATA_UNSIGN
0-1
0
0: Signed input data.
1: Unsigned input data.
DATA_WIDTH
2-18
12
Data bit width. Signed data width ranges from 2 to 18 bits; unsigned from
2 to 17 bits.
SYSTOLIC
VALID_O
CoreFIR v8.5 Handbook
0-1
0-1
0
1
Folded filter does not use the parameter.
Folded filter does not use the parameter.
25
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